Continuous-time (CT) Sigma Delta (ΣΔ) analog-to-digital converters (ADC) have received much attention in the last couple of years for applications that require signal bandwidths of several MHz. Continuous-time ADCs are more favourable over switched-capacitor ADCs due to their lower power requirements. Other advantages include better noise immunity due to their inherent anti-aliasing properties, which is especially advantageous in RF receivers. Also, the technology trend towards very deep submicron processes dictates lower power supply voltages. As a consequence, switched capacitor based circuits require boot-strapping techniques to drive the switches in order to extend the dynamic range and sampling rates of the converter. Continuous-time ADCs avoid such problems and much higher signal bandwidths can be attained.
Despite the advantages mentioned above in using continuous-time ΣΔ ADCs, audio band ADC implementations have remained in the discrete time domain. This is because discrete time ADCs achieve relatively high linearity, they are very tolerant of clock jitter, and as high signal bandwidths are not required moderate sampling rates can be employed in sigma-delta based ADCs. Also, chopper stabilisation can be readily employed in discrete-time to remove the flicker noise especially problematic in deep submicron MOS devices.
A discrete-time ADC implementation would seem to be advantageous over a continuous-time ADC for audio band applications for the reasons just mentioned. However, relatively large signal ranges, e.g. 2 Vrms, used for television audio are outside the voltage range that switched-capacitor based circuits implemented in deep sub-micron process technologies can easily interface to. The input voltage range must be constrained to the allowed limits dictated by the process technology. In this case, the only solution would be to attenuate the input signal and thus surrender valuable dynamic range. Even after attenuating the input signal, anti-alias filtering circuitry and buffering circuitry would be required to drive the switched-capacitor input stage.
OEMs typically demand that this functionality is provided on-chip, inevitably leading to an increased die cost along with deteriorated noise performance.
The motivation for using a continuous-time front-end ΣΔ modulator in this application is that it avoids having to attenuate, anti-alias filter and buffer the input. However, there remain problems in using a continuous-time front-end ΣΔ ADC.
FIG. 1 illustrates a generalized topology as used in a multi-bit sigma delta ADC. In a conventional manner, the multi-level output of the feedback DAC 14 is summed 11 with an input signal 10 and the resulting output is integrated 12. The subsequent integrator stages 16, 17 following the first stage 15 can be continuous-time or discrete-time. A Flash ADC 18 converts the output of the last integrator stage 17 into a multi-bit digital code which is fed back to the DACs within stages 15, 16, 17. A digital filter and decimator 19 converts the output into a digital code having a desired resolution.
In FIG. 1, a single-ended continuous-time (CT) sigma delta ADC input stage 15 requires the use of a single-ended feedback IDAC 14. FIG. 2 illustrates a typical solution, or structure, for a single-ended input continuous-time ADC. This corresponds to stage 15 in FIG. 1. An input signal Vin is converted to a current by resistor Rint which flows into a summing node 21. The feedback path includes a current digital-to-analog converter (IDAC) 22 which comprises a set of 2N unit value current digital-to-analog converters (IDACs) 25, only one of which is shown. The set of IDACs 25 are also connected to the summing node 21. Each IDAC 25 comprises a first branch which is connected to the summing node 21 via a switch 24A and a second branch which is connected to an op-amp 26 via a switch 24B. Each IDAC 25 receives a selection signal D. The selection signal is applied directly to switch 24A and inverted before being applied to switch 24B. An integrator amplifier 27 integrates the output on a continuous basis.
The circuit shown in FIG. 2 has certain disadvantages, including: (1) common-mode noise is not rejected in this single-ended input structure; (2) even harmonics produced in the IDAC are not cancelled; (3) chopping the IDAC current sources, as well as the DC biasing current source flicker noise, is not possible in this single-ended input structure.
The present invention seeks to provide an improved ADC.